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DATE
2010
IEEE
110views Hardware» more  DATE 2010»
14 years 12 days ago
An RDL-configurable 3D memory tier to replace on-chip SRAM
—In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked ...
Marco Facchini, Paul Marchal, Francky Catthoor, Wi...
EMSOFT
2008
Springer
13 years 8 months ago
On the interplay of dynamic voltage scaling and dynamic power management in real-time embedded applications
Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM) are two popular techniques commonly employed to save energy in real-time embedded systems. DVS policies aim at red...
Vinay Devadas, Hakan Aydin
ASPLOS
2010
ACM
14 years 2 months ago
Virtualized and flexible ECC for main memory
We present a general scheme for virtualizing main memory errorcorrection mechanisms, which map redundant information needed to correct errors into the memory namespace itself. We ...
Doe Hyun Yoon, Mattan Erez
CODES
2005
IEEE
14 years 28 days ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
ASPLOS
2012
ACM
12 years 3 months ago
DreamWeaver: architectural support for deep sleep
Numerous data center services exhibit low average utilization leading to poor energy efficiency. Although CPU voltage and frequency scaling historically has been an effective mea...
David Meisner, Thomas F. Wenisch