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ICS
2003
Tsinghua U.
14 years 15 days ago
Reducing register ports using delayed write-back queues and operand pre-fetch
In high-performance wide-issue microprocessors the access time, energy and area of the register file are often critical to overall performance. This is because these pararmeters g...
Nam Sung Kim, Trevor N. Mudge
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 26 days ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
ASPDAC
2009
ACM
110views Hardware» more  ASPDAC 2009»
14 years 1 months ago
A software solution for dynamic stack management on scratch pad memory
Abstract— In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed instead of caches, which can consume majority of processor power. Howe...
Arun Kannan, Aviral Shrivastava, Amit Pabalkar, Jo...
NLDB
2001
Springer
13 years 11 months ago
"Where Are the Christmas Decorations?": A Memory Assistant for Storage Locations
At Hewlett-Packard Laboratories we want to know how inexpensive it can be to endow mobile personal assistants with the ability to speak naturally with their users. To this end, we ...
Lewis G. Creary, Michael VanHilst
CORR
2010
Springer
177views Education» more  CORR 2010»
13 years 4 months ago
Dynamic Scheduling of Skippable Periodic Tasks with Energy Efficiency in Weakly Hard Real-Time System
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...
Santhi Baskaran, P. Thambidurai