7 search results - page 2 / 2 » Using on-chip test pattern compression for full scan SoC des... |
DATE
2003
IEEE
14 years 20 days ago
2003
IEEE
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...