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» Using the DEVS Paradigm to Implement a Simulated Processor
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CODES
2011
IEEE
12 years 8 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
ISLPED
2003
ACM
86views Hardware» more  ISLPED 2003»
14 years 2 months ago
Exploiting compiler-generated schedules for energy savings in high-performance processors
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...
Madhavi Gopal Valluri, Lizy Kurian John, Heather H...
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
14 years 2 months ago
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmo...
IPPS
2005
IEEE
14 years 2 months ago
Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors
As energy consumption in high-performance systems has increased, thermal management has become a big challenge. Providing a cost-effective and detailed temperature sensing mechani...
Kyeong-Jae Lee, Kevin Skadron
CG
2007
Springer
13 years 8 months ago
Fast continuous collision detection among deformable models using graphics processors
We present an interactive algorithm to perform continuous collision detection between general deformable models using graphics processors (GPUs). We model the motion of each objec...
Naga K. Govindaraju, Ilknur Kabul, Ming C. Lin, Di...