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» Using the DEVS Paradigm to Implement a Simulated Processor
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DATE
2002
IEEE
146views Hardware» more  DATE 2002»
14 years 1 months ago
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
To enable fast and accurate evaluation of HW/SW implementation choices of on-chip communication, we present a method to automatically generate timed OS simulation models. The meth...
Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, A...
VLSID
2000
IEEE
164views VLSI» more  VLSID 2000»
14 years 1 months ago
A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation
Digital images are convenient media for describing and storing spatial, temporal, spectral, and physical components of information contained in a variety of domains(e.g. aerial/sa...
Sabyasachi Dey, Bhargab B. Bhattacharya, Malay Kum...
ARITH
2001
IEEE
14 years 11 days ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee
DAC
2002
ACM
14 years 9 months ago
Software synthesis from synchronous specifications using logic simulation techniques
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
Yunjian Jiang, Robert K. Brayton
IPPS
1997
IEEE
14 years 28 days ago
Parallel Simulated Annealing: An Adaptive Approach
This paper analyses alternatives for the parallelization of the Simulated Annealing algorithm when applied to the placement of modules in a VLSI circuit considering the use of PVM...
Jonas Knopman, Júlio S. Aude