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» Using the DEVS Paradigm to Implement a Simulated Processor
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MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
13 years 8 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
APCSAC
2001
IEEE
14 years 14 days ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
14 years 3 months ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
HPCA
2012
IEEE
12 years 4 months ago
Flexible register management using reference counting
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We ...
Steven Battle, Andrew D. Hilton, Mark Hempstead, A...
ICANNGA
2007
Springer
14 years 3 months ago
DNA Based Evolutionary Approach for Microprocessor Design Automation
In a paper [1] presented to BICS 2006, a basic methodology for microprocessor design automation using DNA sequences was proposed. A refined methodology with new schemes for travers...
Nagarajan Venkateswaran, Arjun Kumeresh, Harish Ch...