Sciweavers

467 search results - page 80 / 94
» Using the DEVS Paradigm to Implement a Simulated Processor
Sort
View
CGO
2008
IEEE
14 years 2 months ago
Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt...
CLADE
2003
IEEE
14 years 26 days ago
vGrid: A Framework For Building Autonomic Applications
With rapid technological advances in network infrastructure, programming languages, compatible component interfaces and so many more areas, today the computational Grid has evolve...
Bithika Khargharia, Salim Hariri, Manish Parashar,...
NOCS
2009
IEEE
14 years 2 months ago
Silicon-photonic clos networks for global on-chip communication
Future manycore processors will require energyefficient, high-throughput on-chip networks. Siliconphotonics is a promising new interconnect technology which offers lower power, h...
Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Sco...
DSN
2005
IEEE
14 years 1 months ago
Defeating Memory Corruption Attacks via Pointer Taintedness Detection
Most malicious attacks compromise system security through memory corruption exploits. Recently proposed techniques attempt to defeat these attacks by protecting program control da...
Shuo Chen, Jun Xu, Nithin Nakka, Zbigniew Kalbarcz...
ISCA
2005
IEEE
126views Hardware» more  ISCA 2005»
14 years 1 months ago
A Tree Based Router Search Engine Architecture with Single Port Memories
Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this resul...
Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Su...