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GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
14 years 24 days ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
NPL
1998
133views more  NPL 1998»
13 years 7 months ago
Parallel Coarse Grain Computing of Boltzmann Machines
Abstract. The resolution of combinatorial optimization problems can greatly benefit from the parallel and distributed processing which is characteristic of neural network paradigm...
Julio Ortega, Ignacio Rojas, Antonio F. Día...
CSUR
2006
147views more  CSUR 2006»
13 years 7 months ago
A survey of research and practices of Network-on-chip
resents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. ...
Tobias Bjerregaard, Shankar Mahadevan
HEURISTICS
2002
99views more  HEURISTICS 2002»
13 years 7 months ago
Parallelizing Tabu Search on a Cluster of Heterogeneous Workstations
In this paper, we present the parallelization of tabu search on a network of workstations using PVM. Two parallelization strategies are integrated: functional decomposition strate...
Ahmad A. Al-Yamani, Sadiq M. Sait, Habib Youssef, ...
VLSI
2005
Springer
14 years 1 months ago
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs
This work addresses the problem of application mapping in networks-on-chip (NoCs) having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (So...
César A. M. Marcon, José Carlos S. P...