70 search results - page 4 / 14 » VLSI Implementation of a Fault-Tolerant Distributed Clock Ge... |
ARVLSI
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves ...
GLVLSI
2003
IEEE
14 years 22 days ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
TVLSI
2002
13 years 7 months ago
2002
A summary of electrical and optical approaches to clock distribution within high-performance microprocessors is presented. System-level properties of intrachip electrical clock dis...
ISVLSI
2003
IEEE
14 years 21 days ago
2003
IEEE
Abstract— Dissipation in the clock tree and state elements of ASIC designs is often a significant fraction of total energy consumption. We propose a methodology for recovering m...
RSP
2003
IEEE
14 years 21 days ago
2003
IEEE
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...