5 search results - page 1 / 1 » VLSI on-chip power ground network optimization considering d... |
ASPDAC
2005
ACM
14 years 4 months ago
2005
ACM
－ In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leak...
ICCD
2007
IEEE
14 years 7 months ago
2007
IEEE
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
ASPDAC
2007
ACM
14 years 2 months ago
2007
ACM
- This paper proposes a fast and practical decoupling capacitor (decap) budgeting algorithm to optimize the power ground (P/G) network design. The new method adopts a modified rand...
ICCD
2006
IEEE
14 years 7 months ago
2006
IEEE
-- Power-gating is a technique for efficiently reducing leakage power by shutting off the idle blocks. However, the presence of power-gating may also introduce negative effects on ...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
- The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce subthreshol...