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124
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ICCAD
2010
IEEE
141views Hardware» more  ICCAD 2010»
15 years 16 days ago
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, ...
119
Voted
INFOCOM
2010
IEEE
15 years 14 days ago
Optimal Solutions for Single Fault Localization in Two Dimensional Lattice Networks
Abstract--Achieving fast, precise, and scalable fault localization has long been a highly desired feature in all-optical mesh networks. Monitoring tree (m-tree) is an interesting m...
János Tapolcai, Lajos Rónyai, Pin-Ha...
187
Voted
TCAD
2010
154views more  TCAD 2010»
14 years 9 months ago
Automated Design Debugging With Maximum Satisfiability
As contemporary VLSI designs grow in complexity, design debugging has rapidly established itself as one of the largest bottlenecks in the design cycle today. Automated debug soluti...
Yibin Chen, Sean Safarpour, João Marques-Si...
110
Voted
TVLSI
2010
14 years 9 months ago
Pattern Sensitive Placement Perturbation for Manufacturability
The gap between VLSI technology and fabrication technology leads to strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features...
Shiyan Hu, Patrik Shah, Jiang Hu
VLSID
2010
IEEE
170views VLSI» more  VLSID 2010»
14 years 8 months ago
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Contro
The continuous increase of leakage power consumption in deep sub-micro technologies necessitates more aggressive leakage control. Runtime leakage control (RTLC) is effective, si...
Hao Xu, Wen-Ben Jone, Ranga Vemuri