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» Valid inequalities for mixed integer linear programs
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ASPDAC
2006
ACM
119views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Using speculative computation and parallelizing techniques to improve scheduling of control based designs
Recent research results have seen the application of parallelizing techniques to high-level synthesis. In particular, the effect of speculative code transformations on mixed contr...
Roberto Cordone, Fabrizio Ferrandi, Marco D. Santa...
ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
14 years 1 months ago
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
Ruibing Lu, Cheng-Kok Koh
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
14 years 24 days ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes
ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
14 years 19 days ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
ICCD
1995
IEEE
83views Hardware» more  ICCD 1995»
14 years 6 days ago
Concurrent timing optimization of latch-based digital systems
Many design techniques have been proposed to optimize the performance of a digital system implemented in a given technology. Each of these techniques can be advantageous in partic...
Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C...