Sciweavers

428 search results - page 22 / 86
» Validating High-Level Synthesis
Sort
View
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 7 months ago
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhi...
ISPD
2012
ACM
252views Hardware» more  ISPD 2012»
12 years 6 months ago
Towards layout-friendly high-level synthesis
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
Jason Cong, Bin Liu 0006, Guojie Luo, Raghu Prabha...
CODES
2000
IEEE
14 years 3 months ago
Automatic test bench generation for simulation-based validation
In current design practice synthesis tools play a key role, letting designers to concentrate on the specificationof the system being designed by carrying out repetitive tasks such...
Marcello Lajolo, Luciano Lavagno, Maurizio Rebaude...
VISUAL
1999
Springer
14 years 3 months ago
Generic Viewer Interaction Semantics for Dynamic Virtual Video Synthesis
The FRAMES project is developing a system for video database search, content-based retrieval, and virtual video program synthesis. For dynamic synthesis applications, a video progr...
Craig A. Lindley, Anne-Marie Vercoustre
FPL
2009
Springer
132views Hardware» more  FPL 2009»
14 years 2 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem