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» Validating High-Level Synthesis
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DATE
2009
IEEE
176views Hardware» more  DATE 2009»
14 years 5 months ago
Automated synthesis of streaming C applications to process networks in hardware
Abstract—The demand for embedded computing power is continuously increasing and FPGAs are becoming very interesting computing platforms, as they provide huge amounts of customiza...
Sven van Haastregt, Bart Kienhuis
ICS
2005
Tsinghua U.
14 years 4 months ago
Improved automatic testcase synthesis for performance model validation
Performance simulation tools must be validated during the design process as functional models and early hardware are developed, so that designers can be sure of the performance of...
Robert H. Bell Jr., Lizy Kurian John
ISPASS
2006
IEEE
14 years 5 months ago
Automatic testcase synthesis and performance model validation for high performance PowerPC processors
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John,...
CLEF
2008
Springer
14 years 22 days ago
Information Synthesis for Answer Validation
This report is about our participation in the Answer Validation Exercise (AVE2008). Our system casts the AVE task into a Recognizing Textual Entailment (RTE) problem and uses an ex...
Rui Wang 0005, Günter Neumann
VLSID
2005
IEEE
87views VLSI» more  VLSID 2005»
14 years 11 months ago
Synthesis of Asynchronous Circuits Using Early Data Validity
Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable stat...
Nitin Gupta, Doug A. Edwards