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» Validating High-Level Synthesis
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FPL
2003
Springer
95views Hardware» more  FPL 2003»
14 years 4 months ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
CEC
2008
IEEE
14 years 5 months ago
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis
— The high-level synthesis process involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the ...
Christian Pilato, Daniele Loiacono, Fabrizio Ferra...
ASPDAC
2005
ACM
146views Hardware» more  ASPDAC 2005»
14 years 28 days ago
High-level synthesis for DSP applications using heterogeneous functional units
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edw...
OOPSLA
2010
Springer
13 years 9 months ago
A simple inductive synthesis methodology and its applications
Given a high-level specification and a low-level programming language, our goal is to automatically synthesize an efficient program that meets the specification. In this paper,...
Shachar Itzhaky, Sumit Gulwani, Neil Immerman, Moo...
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
14 years 11 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan