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» Validating High-Level Synthesis
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VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
14 years 5 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
CASES
2008
ACM
14 years 29 days ago
Optimus: efficient realization of streaming applications on FPGAs
In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either so...
Amir Hormati, Manjunath Kudlur, Scott A. Mahlke, D...
CSL
2006
Springer
14 years 2 months ago
Church Synthesis Problem with Parameters
For a two-variable formula (X, Y ) of Monadic Logic of Order (MLO) the Church Synthesis Problem concerns the existence and construction of an operator Y = F(X) such that (X, F(X)) ...
Alexander Moshe Rabinovich
DATE
2009
IEEE
120views Hardware» more  DATE 2009»
14 years 5 months ago
Optimizing data flow graphs to minimize hardware implementation
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, ...
SIES
2007
IEEE
14 years 5 months ago
Design Space Exploration with Evolutionary Multi-Objective Optimisation
— High level synthesis is one of the next major steps to improve the hw/sw co-design process. The advantages of high nthesis are two-fold. At first the level of abstraction is r...
Martin Holzer 0002, Bastian Knerr, Markus Rupp