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» Validating High-Level Synthesis
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DATE
2006
IEEE
127views Hardware» more  DATE 2006»
14 years 5 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...
RSP
2006
IEEE
102views Control Systems» more  RSP 2006»
14 years 5 months ago
Rapid Resource-Constrained Hardware Performance Estimation
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrish...
VLSI
2005
Springer
14 years 4 months ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...
FASE
2003
Springer
14 years 4 months ago
Detecting Implied Scenarios Analyzing Non-local Branching Choices
Scenarios are powerful tools to model and analyze software systems. However, since they do not provide a complete description of the system, but just some possible execution paths,...
Henry Muccini
ICCAD
1991
IEEE
76views Hardware» more  ICCAD 1991»
14 years 2 months ago
Flexible Block-Multiplier Generation
In a high level synthesis environment there is a strong need for flexible module generators. For the generation of regular structures efficient dedicated module generators can be ...
H. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon S...