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HIPEAC
2010
Springer
13 years 11 months ago
Computer Generation of Efficient Software Viterbi Decoders
This paper presents a program generator for fast software Viterbi decoders for arbitrary convolutional codes. The input to the generator is a specification of the code and a single...
Frédéric de Mesmay, Srinivas Chellap...
IEEEPACT
2008
IEEE
14 years 3 months ago
Exploiting loop-dependent stream reuse for stream processors
The memory access limits the performance of stream processors. By exploiting the reuse of data held in the Stream Register File (SRF), an on-chip storage, the number of memory acc...
Xuejun Yang, Ying Zhang, Jingling Xue, Ian Rogers,...
IPPS
2003
IEEE
14 years 2 months ago
SPMD Image Processing on Beowulf Clusters: Directives and Libraries
Most image processing algorithms can be parallelized by splitting parallel loops and by using very few communication patterns. Code parallelization using MPI still involves much p...
Paulo F. Oliveira, J. M. Hans du Buf
FPL
2009
Springer
161views Hardware» more  FPL 2009»
14 years 1 months ago
A multi-FPGA architecture for stochastic Restricted Boltzmann Machines
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
Daniel L. Ly, Paul Chow
ISLPED
2007
ACM
84views Hardware» more  ISLPED 2007»
13 years 10 months ago
Towards a software approach to mitigate voltage emergencies
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. One a...
Meeta Sharma Gupta, Krishna K. Rangan, Michael D. ...