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» Validation and test generation for oscillatory noise in VLSI...
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ICCAD
1999
IEEE
72views Hardware» more  ICCAD 1999»
14 years 3 months ago
Validation and test generation for oscillatory noise in VLSI interconnects
: Inductance of on-chip interconnects gives rise to signal overshoots and undershoots that can cause logic errors. By considering technology trends, we show that in 0.13
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
14 years 3 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey
TCAD
2002
115views more  TCAD 2002»
13 years 10 months ago
Analytical models for crosstalk excitation and propagation in VLSI circuits
We develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupli...
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
DAC
2008
ACM
14 years 11 months ago
On reliable modular testing with vulnerable test access mechanisms
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...
Lin Huang, Feng Yuan, Qiang Xu
TODAES
2002
134views more  TODAES 2002»
13 years 10 months ago
False-noise analysis using logic implications
ct Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneousl...
Alexey Glebov, Sergey Gavrilov, David Blaauw, Vlad...