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ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
14 years 10 days ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
ASPDAC
2004
ACM
94views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Improving simulation-based verification by means of formal methods
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
Görschwin Fey, Rolf Drechsler
FMICS
2009
Springer
14 years 2 months ago
Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models
Cell libraries often contain a simulation model in a system design language, such as Verilog. These languages usually involve nondeterminism, which in turn, poses a challenge to th...
Matthias Raffelsieper, Mohammad Reza Mousavi, Jan-...
RTCSA
1997
IEEE
13 years 11 months ago
Behavior verification of hybrid real-time requirements by qualitative formalism
Although modern control theories have been successfully applied to solve a variety of problems, they are often mathematically and physically too specific to describe and analyze t...
Jang-Soo Lee, Sung Deok Cha
IFM
2007
Springer
245views Formal Methods» more  IFM 2007»
14 years 1 months ago
Co-simulation of Distributed Embedded Real-Time Control Systems
Development of computerized embedded control systems is difficult because it brings together systems theory, electrical engineering and computer science. The engineering and analys...
Marcel Verhoef, Peter Visser, Jozef Hooman, Jan F....