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» Variation-aware routing for FPGAs
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ICES
2005
Springer
177views Hardware» more  ICES 2005»
14 years 1 months ago
Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs
Evolvable Hardware arises as a promising solution for automatic digital synthesis of digital and analog circuits. During the last decade, a special interest has been focused on evo...
Andres Upegui, Eduardo Sanchez
DATE
2003
IEEE
69views Hardware» more  DATE 2003»
14 years 23 days ago
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...
Ulrich Seidl, Klaus Eckl, Frank M. Johannes
FPGA
1997
ACM
142views FPGA» more  FPGA 1997»
13 years 11 months ago
Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond
Process technology advances tell us that the one-million gate Field-Programmable Gate Array (FPGA) will soon be here, and larger devices shortly after that. We feel that current a...
Jonathan Rose, Dwight D. Hill
FPGA
1997
ACM
168views FPGA» more  FPGA 1997»
13 years 11 months ago
Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays
This paper shows that the speed of FPGAs with large embedded memory arrays can be improved by adding direct programmable connections between the memories. Nets that connect to mul...
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vran...
MAM
2006
95views more  MAM 2006»
13 years 7 months ago
Stochastic spatial routing for reconfigurable networks
FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle pr...
André DeHon, Randy Huang, John Wawrzynek