226 search results - page 19 / 46 » Variation-tolerant circuits: circuit solutions and technique... |
FPL
2006
Springer
14 years 3 days ago
2006
Springer
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
This paper presents a power grid analyzer based on a random walk technique. A linear-time algorithm is first demonstrated for DC analysis, and is then extended to perform transien...
ATS
2010
IEEE
13 years 6 months ago
2010
IEEE
One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speedpaths in the circuit under debug (CUD) and o...
Publication
A large class of systems of biological and technological relevance can be described as analog networks, that is, collections of dynamic devices interconnected by links of varying s...
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
- In this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running...