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» Variation-tolerant circuits: circuit solutions and technique...
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ASPDAC
2009
ACM
127views Hardware» more  ASPDAC 2009»
14 years 1 months ago
Timing driven power gating in high-level synthesis
- The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...
Shih-Hsu Huang, Chun-Hua Cheng
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
14 years 1 months ago
A multi-core debug platform for NoC-based systems
Network-on-Chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in gigascale integrated circuits. As traditional debug archi...
Shan Tang, Qiang Xu
BROADNETS
2006
IEEE
13 years 11 months ago
On Traffic Grooming Choices for IP over WDM networks
Traffic grooming continues to be a rich area of research in the context of WDM optical networks. We provide an overview of the optical and electronic grooming techniques available...
Srivatsan Balasubramanian, Arun K. Somani
INFOCOM
2010
IEEE
13 years 5 months ago
Analyzing Nonblocking Switching Networks using Linear Programming (Duality)
Abstract—The main task in analyzing a switching network design (including circuit-, multirate-, and photonic-switching) is to determine the minimum number of some switching compo...
Hung Q. Ngo, Atri Rudra, Anh N. Le, Thanh-Nhan Ngu...
DAC
2002
ACM
14 years 8 months ago
Embedded software-based self-testing for SoC design
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li...