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» Vdd programmability to reduce FPGA interconnect power
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FPL
2008
Springer
125views Hardware» more  FPL 2008»
14 years 12 days ago
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks
FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconf...
Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dud...
ISCAS
2008
IEEE
103views Hardware» more  ISCAS 2008»
14 years 5 months ago
A low-power monolithically stacked 3D-TCAM
—This paper presents three techniques to reduce the power consumption in ternary content-addressable memories (TCAMs). The first technique is to use newly developed monolithical...
Mingjie Lin, Jianying Luo, Yaling Ma
ICCD
2004
IEEE
97views Hardware» more  ICCD 2004»
14 years 7 months ago
A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been...
John Lach, Jason Brandon, Kevin Skadron
ICRA
2006
IEEE
158views Robotics» more  ICRA 2006»
14 years 4 months ago
An Agent-based Mobile Robot System using Configurable SOC Technique
– To make a mobile robot with real-time vision system adapt to the highly dynamic environments and emergencies under the real-time constraints, a significant account of processin...
Yan Meng
DAC
2002
ACM
14 years 11 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik