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MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
ASR: Adaptive Selective Replication for CMP Caches
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
Bradford M. Beckmann, Michael R. Marty, David A. W...
ETRA
2006
ACM
198views Biometrics» more  ETRA 2006»
14 years 1 months ago
Perceptual attention focus prediction for multiple viewers in case of multimedia perceptual compression with feedback delay
Human eyes have limited perception capabilities. Only 2 degrees of our 180 degree vision field provide the highest quality of perception. Due to this fact the idea of perceptual a...
Oleg Komogortsev, Javed I. Khan
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 15 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
14 years 10 days ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
ICNP
2000
IEEE
13 years 11 months ago
Differentiated Predictive Fair Service for TCP Flows
The majority of the traffic (bytes) flowing over the Internet today have been attributed to the Transmission Control Protocol (TCP). This strong presence of TCP has recently spu...
Ibrahim Matta, Liang Guo