Sciweavers

714 search results - page 117 / 143
» Verification and Compliance Testing
Sort
View
HPCA
2009
IEEE
14 years 9 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
POPL
2005
ACM
14 years 9 months ago
Mutatis mutandis: safe and predictable dynamic software updating
Dynamic software updates can be used to fix bugs or add features to a running program without downtime. Essential for some applications and convenient for others, low-level dynami...
Gareth Stoyle, Michael W. Hicks, Gavin M. Bierman,...
ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
14 years 1 months ago
Vectorless Analysis of Supply Noise Induced Delay Variation
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...
WETICE
2000
IEEE
14 years 1 months ago
Reducing Software Security Risk through an Integrated Approach
This paper presents joint work by the California Institute of Technology’s Jet Propulsion Laboratory and the University of California at Davis (UC Davis) sponsored by the Nation...
David P. Gilliam, John C. Kelly, Matt Bishop
RTSS
1998
IEEE
14 years 26 days ago
Membership Questions for Timed and Hybrid Automata
Timed and hybrid automata are extensions of finite-state machines for formal modeling of embedded systems with both discrete and continuous components. Reachability problems for t...
Rajeev Alur, Robert P. Kurshan, Mahesh Viswanathan