169 search results - page 31 / 34 » Verification of Dynamically Reconfigurable Logic |
AOSD
2008
ACM
13 years 9 months ago
2008
ACM
Many aspect-oriented middleware platforms support run-time aspect weaving, but do not support coordinating distributed changes to a set of aspects at run-time. A distributed chang...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
EMSOFT
2006
Springer
13 years 11 months ago
2006
Springer
We report on a case study in which the model checker Uppaal is used to formally model parts of Zeroconf, a protocol for dynamic configuration of IPv4 link-local addresses that has...
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
POPL
2009
ACM
14 years 8 months ago
2009
ACM
ibe an abstract interpretation based framework for proving relationships between sizes of memory partitions. Instances of this framework can prove traditional properties such as m...