37 search results - page 3 / 8 » Verification of Floating-Point Adders |
ARITH
2003
IEEE
14 years 25 days ago
2003
IEEE
This work uses a partially redundant number system as an internal format for floating point arithmetic operations. The redundant number system enables carry free arithmetic opera...
CJ
2010
13 years 7 months ago
2010
rder logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, ...
ARITH
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— Floating-point arithmetic is notoriously nonassociative due to the limited precision representation which demands intermediate values be rounded to fit in the availabl...
ARITH
1999
IEEE
13 years 12 months ago
1999
IEEE
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the...
TPHOL
1999
IEEE
13 years 11 months ago
1999
IEEE
Abstract. Intel is applying formal verification to various pieces of mathematical software used in Merced, the first implementation of the new IA-64 architecture. This paper discus...