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» Verification of Floating-Point Adders
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TPHOL
2000
IEEE
13 years 11 months ago
Formal Verification of IA-64 Division Algorithms
The IA-64 architecture defers floating point and integer division to software. To ensure correctness and maximum efficiency, Intel provides a number of recommended algorithms which...
John Harrison
DATE
2004
IEEE
89views Hardware» more  DATE 2004»
13 years 11 months ago
Improved Symoblic Simulation by Dynamic Funtional Space Partitioning
In this paper, we provide a flexible and automatic method to partition the functional space for efficient symbolic simulation. We utilize a 2-tuple list representation as the basi...
Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan ...
CIT
2006
Springer
13 years 11 months ago
Design of Novel Reversible Carry Look-Ahead BCD Subtractor
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard. A major enhancement to the standard is the addition of decimal format, thus the design of BCD arithmetic...
Himanshu Thapliyal, Sumedha K. Gupta
DAC
2008
ACM
14 years 8 months ago
Construction of concrete verification models from C++
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, ...
ACL2
2006
ACM
13 years 11 months ago
Combining ACL2 and an automated verification tool to verify a multiplier
We have extended the ACL2 theorem prover to automatically prove properties of VHDL circuits with IBM's Internal SixthSense verification system. We have used this extension to...
Erik Reeber, Jun Sawada