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» Verification of System Level Model Transformations
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CAISE
2006
Springer
15 years 6 months ago
Modelling and Verifying of e-Commerce Systems
Static function hierarchies and models of the dynamic behaviour are typically used in e-commerce systems. Issues to be verifies are the completeness and correctness of the static f...
Andreas Speck
TODAES
1998
68views more  TODAES 1998»
15 years 2 months ago
Specification and verification of pipelining in the ARM2 RISC microprocessor
Abstract State Machines (ASMs) provide a sound mathematical basis for the specification and verification of systems. An application of the ASM methodology to the verification of a ...
James K. Huggins, David Van Campenhout
ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
15 years 7 days ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
130
Voted
VLSID
2003
IEEE
253views VLSI» more  VLSID 2003»
16 years 2 months ago
High Level Synthesis from Sim-nML Processor Models
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
Souvik Basu, Rajat Moona
DATE
2008
IEEE
102views Hardware» more  DATE 2008»
15 years 9 months ago
Semantics for Model-Based Validation of Continuous/Discrete Systems
Continuous and discrete components can be integrated in diverse systems including defense, medical, electronic, communication, and automotive applications. Given the heterogeneity...
Luiza Gheorghe, Faouzi Bouchhima, Gabriela Nicoles...