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» Verification of System Level Model Transformations
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158
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SBCCI
2003
ACM
135views VLSI» more  SBCCI 2003»
15 years 7 months ago
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectur...
Mauricio Ayala-Rincón, Rodrigo B. Nogueira,...
128
Voted
VIS
2006
IEEE
157views Visualization» more  VIS 2006»
16 years 3 months ago
Analyzing Complex FTMS Simulations: a Case Study in High-Level Visualization of Ion Motions
Current practice in particle visualization renders particle position data directly onto the screen as points or glyphs. Using a camera placed at a fixed position, particle motions...
Wojciech Burakiewicz, Robert van Liere
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
15 years 6 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
IPPS
2007
IEEE
15 years 9 months ago
Simulating Red Storm: Challenges and Successes in Building a System Simulation
Supercomputers are increasingly complex systems merging conventional microprocessors with system on a chip level designs that provide the network interface and router. At Sandia N...
Keith D. Underwood, Michael Levenhagen, Arun Rodri...
DT
2006
180views more  DT 2006»
15 years 2 months ago
A SystemC Refinement Methodology for Embedded Software
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
Jérôme Chevalier, Maxime de Nanclas, ...