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» Verification of Timed Systems Using POSETs
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DAC
2006
ACM
14 years 8 months ago
Scheduling-based test-case generation for verification of multimedia SoCs
Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which is in charge of a stage in the processing of a media stream. The v...
Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ron...
DAC
2008
ACM
14 years 8 months ago
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts
End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In t...
Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. R...
TII
2008
98views more  TII 2008»
13 years 7 months ago
Formal Methods for Systems Engineering Behavior Models
Abstract--Safety analysis in Systems Engineering (SE) processes, as usually implemented, rarely relies on formal methods such as model checking since such techniques, however power...
Charlotte Seidner, Olivier H. Roux
ICPR
2004
IEEE
14 years 8 months ago
Competitive Coding Scheme for Palmprint Verification
There is increasing interest in the development of reliable, rapid and non-intrusive security control systems. Among the many approaches, biometrics such as palmprints provide hig...
Adams Wai-Kin Kong, David Zhang
ICCAD
1994
IEEE
65views Hardware» more  ICCAD 1994»
13 years 11 months ago
Incremental formal design verification
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
Gitanjali Swamy, Robert K. Brayton