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» Verification of Timed Systems Using POSETs
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DATE
2003
IEEE
134views Hardware» more  DATE 2003»
14 years 21 days ago
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Ri...
SSS
2010
Springer
125views Control Systems» more  SSS 2010»
13 years 5 months ago
Systematic Correct Construction of Self-stabilizing Systems: A Case Study
Design and implementation of distributed algorithms often involve many subtleties due to their complex structure, non-determinism, and low atomicity as well as occurrence of unanti...
Ananda Basu, Borzoo Bonakdarpour, Marius Bozga, Jo...
ASPDAC
2004
ACM
94views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Improving simulation-based verification by means of formal methods
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
Görschwin Fey, Rolf Drechsler
FORMATS
2010
Springer
13 years 5 months ago
Layered Composition for Timed Automata
Abstract. We investigate layered composition for real-time systems modelled as (networks of) timed automata (TA). We first formulate the principles of layering and transition indep...
Ernst-Rüdiger Olderog, Mani Swaminathan
FMCAD
2006
Springer
13 years 11 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar