196 search results - page 4 / 40 » Verification of timing Properties of VHDL |
ASYNC
2000
IEEE
14 years 23 hour ago
2000
IEEE
JUCS
2006
13 years 7 months ago
2006
: The size and complexity of software systems are continuously increasing, which makes them difficult and labor-intensive to develop, test and evolve. Since concurrent systems are ...
CONIELECOMP
2011
IEEE
12 years 11 months ago
2011
IEEE
This work focuses on developing systems of blocks in SIMULINK and VHDL to reuse on design of applications involving the recognition of polygonal objects. Usage of this work reduce...
ICLP
2010
Springer
2010
Springer
A Framework for Verification and Debugging of Resource Usage Properties: Resource Usage Verification
13 years 5 months ago
We present a framework for (static) verification of general resource usage program properties. The framework extends the criteria of correctness as the conformance of a program to ...
ACL2
2006
ACM
13 years 11 months ago
2006
ACM
We have extended the ACL2 theorem prover to automatically prove properties of VHDL circuits with IBM's Internal SixthSense verification system. We have used this extension to...