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ICCD
2007
IEEE
106views Hardware» more  ICCD 2007»
13 years 11 months ago
Transparent mode flip-flops for collapsible pipelines
Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in moder...
Eric L. Hill, Mikko H. Lipasti
GLVLSI
2009
IEEE
113views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Reducing parity generation latency through input value aware circuits
1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit ...
Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz ...
APCSAC
2004
IEEE
13 years 11 months ago
A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking
As device sizes continue shrinking, lower charges are needed to activate gates, and consequently ever smaller external events (such as single ionizing particles of naturally occurr...
Xiaobin Li, Jean-Luc Gaudiot
ASAP
2004
IEEE
140views Hardware» more  ASAP 2004»
13 years 11 months ago
Decimal Floating-Point Division Using Newton-Raphson Iteration
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...
Liang-Kai Wang, Michael J. Schulte
CSB
2004
IEEE
108views Bioinformatics» more  CSB 2004»
13 years 11 months ago
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA
Our previous work to accelerate phylogeny inference using HW/SW(Hardware/Software) co-design has recently been extended to a more powerful embedded computing platform. In this pla...
Terrence S. T. Mak, Kai-Pui Lam