584 search results - page 67 / 117 » Verification-Aware Microprocessor Design |
CODES
1999
IEEE
14 years 4 days ago
1999
IEEE
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important as...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
Reconfigurable Computers based on a combination of conventional microprocessors and Field Programmable Gate Arrays (FPGAs) presents new challenges to designers. Debugging on such ...