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DATE
2004
IEEE
164views Hardware» more  DATE 2004»
14 years 20 days ago
System Design Using Kahn Process Networks: The Compaan/Laura Approach
New emerging embedded system platforms in the realm of highthroughput multimedia, imaging, and signal processing will consist of multiple microprocessors and reconfigurable compon...
Todor Stefanov, Claudiu Zissulescu, Alexandru Turj...
VLSISP
2008
93views more  VLSISP 2008»
13 years 8 months ago
Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path
The speedups and the energy reductions achieved in a generic single-chip microprocessor system by employing a high-performance data-path are presented. The data-path acts as a copr...
Michalis D. Galanis, Gregory Dimitroulakos, Costas...
ICCD
1997
IEEE
90views Hardware» more  ICCD 1997»
14 years 14 days ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta...
CDES
2006
78views Hardware» more  CDES 2006»
13 years 10 months ago
The Impact of Cache Organization in Optimizing Microprocessor Power Consumption
In the recent years, power consumption has become increasingly an important design concern as silicon area and performance in modern computer systems design. Several factors have ...
Nagm Mohamed, Nazeih Botros, Wei Zhang
DAC
2004
ACM
14 years 20 days ago
A dual-core 64b ultraSPARC microprocessor for dense server applications
A processor core, previously implemented in a 0.25m Al process, is redesigned for a 0.13m Cu process to create a dualcore processor with 1MB integrated L2 cache, offering an effic...
Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petri...