The Impact of Cache Organization in Optimizing Microprocessor Power Consumption

In the recent years, power consumption has become increasingly an important design concern as silicon area and performance in modern computer systems design. Several factors have contributed to this trend. Perhaps the most visible have been the remarkable success and growth of Personal Digital Assistants (PDA's), Cellular phones and pagers, etc .This work is an attempt to explore the impact of feature size shrinkage and cache configuration on optimizing power consumption in modern processors. The work studies two commercially known RISC micro- processors. The StrongARM and the Alpha-21064 microprocessors. The latter is the ancestor of the former and is therefore used here as the baseline in our analysis. Our analysis has illustrated quantitatively great power saving when technology is downsized and cache is well organized

• Type: Conference
• Year: 2006
• Where: CDES
• Authors: Nagm Mohamed, Nazeih Botros, Wei Zhang
• Keywords: CDES 2006, CDES 2007, Feature Size Shrinkage, Important Design Concern, Power Consumption