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ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
14 years 5 days ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
14 years 1 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
ISCA
2007
IEEE
120views Hardware» more  ISCA 2007»
14 years 2 months ago
Examining ACE analysis reliability estimates using fault-injection
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
HPCA
2007
IEEE
14 years 8 months ago
Implications of Device Timing Variability on Full Chip Timing
As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This pap...
Murali Annavaram, Ed Grochowski, Paul Reed
HPCA
2004
IEEE
14 years 8 months ago
Exploiting Prediction to Reduce Power on Buses
We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified Si...
Victor Wen, Mark Whitney, Yatish Patel, John Kubia...