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» Verification-Aware Microprocessor Design
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DSN
2008
IEEE
14 years 2 months ago
Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors
As semiconductor technology scales, reliability is becoming an increasingly crucial challenge in microprocessor design. The rSRAM and voltage scaling are two promising circuit-lev...
Xin Fu, Tao Li, José A. B. Fortes
IPPS
2007
IEEE
14 years 2 months ago
Simulating Red Storm: Challenges and Successes in Building a System Simulation
Supercomputers are increasingly complex systems merging conventional microprocessors with system on a chip level designs that provide the network interface and router. At Sandia N...
Keith D. Underwood, Michael Levenhagen, Arun Rodri...
ASPDAC
2005
ACM
115views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Low-power domino circuits using NMOS pull-up on off-critical paths
- Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose ...
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij...
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
14 years 1 months ago
Energy reduction in multiprocessor systems using transactional memory
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniproc...
Tali Moreshet, R. Iris Bahar, Maurice Herlihy
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 1 months ago
Instruction packing: reducing power and delay of the dynamic scheduling logic
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghos...