584 search results - page 95 / 117 » Verification-Aware Microprocessor Design |
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, sc...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
Value prediction is a relatively new technique to increase the Instruction Level Parallelism (ILP) in future microprocessors. An important problem when designing a value predictor...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density...