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DSN
2007
IEEE
14 years 2 months ago
Using Register Lifetime Predictions to Protect Register Files against Soft Errors
— Device scaling and large integration increase the vulnerability of microprocessors to transient errors. One of the structures where errors can be most harmful is the register ...
Pablo Montesinos, Wei Liu, Josep Torrellas
DSN
2007
IEEE
14 years 2 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
ICCD
2007
IEEE
182views Hardware» more  ICCD 2007»
14 years 2 months ago
Reducing leakage power in peripheral circuits of L2 caches
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...
Houman Homayoun, Alexander V. Veidenbaum
VTS
2007
IEEE
103views Hardware» more  VTS 2007»
14 years 2 months ago
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester
In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...
Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
VLSI
2007
Springer
14 years 1 months ago
Simulation of hybrid computer architectures: simulators, methodologies and recommendations
— In the future, high performance computing systems may consist of multiple multicore processors and reconfigurable logic coprocessors. Industry trends indicate that such coproc...
Pranav Vaidya, Jaehwan John Lee