118 search results - page 12 / 24 » Verifying Correctness of Transactional Memories |
FORMATS
2006
Springer
13 years 10 months ago
2006
Springer
Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of so...
DSN
2006
IEEE
14 years 23 days ago
2006
IEEE
—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the h...
DATE
2003
IEEE
14 years 13 hour ago
2003
IEEE
The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level a finite set of architecture components (memories, ar...
FAC
2008
13 years 6 months ago
2008
The Mondex case study about the specification and refinement of an electronic purse as defined in the Oxford Technical Monograph PRG-126 has recently been proposed as a challenge f...
VLSID
2001
IEEE
14 years 7 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...