118 search results - page 17 / 24 » Verifying Correctness of Transactional Memories |
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
ASPLOS
2000
ACM
13 years 11 months ago
2000
ACM
This paper describes the architecture and implementation of the AlphaServer GS320, a cache-coherent non-uniform memory access multiprocessor developed at Compaq. The AlphaServer G...
CIDR
2011
12 years 10 months ago
2011
Distributed programming has become a topic of widespread interest, and many programmers now wrestle with tradeoffs between data consistency, availability and latency. Distributed...
MICRO
2010
IEEE
13 years 4 months ago
2010
IEEE
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
HPCA
2007
IEEE
14 years 1 months ago
2007
IEEE
To provide high dependability in a multithreaded system despite hardware faults, the system must detect and correct errors in its shared memory system. Recent research has explore...