1093 search results - page 106 / 219 » Verifying VLSI Circuits |
109
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ISCAS
2005
IEEE
15 years 8 months ago
2005
IEEE
— This paper proposes a novel nonlinear modulating function approach for generating n−scroll chaotic attractors based on a general jerk circuit. The systematic nonlinear modula...
97
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ISCAS
2002
IEEE
15 years 8 months ago
2002
IEEE
On-chip ESD protection circuits realized with novel diode structures without the field-oxide boundary across the p/n junction are proposed. A PMOS (NMOS) is especially inserted in...
102
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DAC
1996
ACM
15 years 7 months ago
1996
ACM
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
131
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CCECE
2011
IEEE
14 years 3 months ago
2011
IEEE
A mode-matching approach is presented for the analysis of substrate-integrated waveguide (SIW) circuits. The numerical technique takes advantage of recently developed fabrication ...
137
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DAC
2007
ACM
16 years 4 months ago
2007
ACM
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...