1093 search results - page 106 / 219 » Verifying VLSI Circuits |
ISCAS
2005
IEEE
14 years 3 months ago
2005
IEEE
— This paper proposes a novel nonlinear modulating function approach for generating n−scroll chaotic attractors based on a general jerk circuit. The systematic nonlinear modula...
ISCAS
2002
IEEE
14 years 3 months ago
2002
IEEE
On-chip ESD protection circuits realized with novel diode structures without the field-oxide boundary across the p/n junction are proposed. A PMOS (NMOS) is especially inserted in...
DAC
1996
ACM
14 years 2 months ago
1996
ACM
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
CCECE
2011
IEEE
12 years 10 months ago
2011
IEEE
A mode-matching approach is presented for the analysis of substrate-integrated waveguide (SIW) circuits. The numerical technique takes advantage of recently developed fabrication ...
DAC
2007
ACM
14 years 11 months ago
2007
ACM
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...