1093 search results - page 139 / 219 » Verifying VLSI Circuits |
GLVLSI
2010
IEEE
14 years 2 months ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
GLVLSI
1998
IEEE
14 years 1 months ago
1998
IEEE
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally u...
BIOSYSTEMS
2007
13 years 9 months ago
2007
10 Phonotaxis is the ability to orient towards or away from sound sources. Crickets can locate conspecifics by phonotaxis to the calling (mating) song they produce, and can evade ...
JCO
2011
13 years 3 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
VLSID
1998
IEEE
14 years 1 months ago
1998
IEEE
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...