1093 search results - page 164 / 219 » Verifying VLSI Circuits |
DAC
2003
ACM
14 years 9 months ago
2003
ACM
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vul...
VLSID
2009
IEEE
14 years 9 months ago
2009
IEEE
Synthesis of reversible logic has become a very important research area. In recent years several algorithms ? heuristic as well as exact ones ? have been introduced in this area. ...
VLSID
2007
IEEE
14 years 9 months ago
2007
IEEE
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...