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» Verifying VLSI Circuits
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DATE
2008
IEEE
75views Hardware» more  DATE 2008»
14 years 3 months ago
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture
To achieve minimum signal propagation delay, the nonuniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploi...
Fu-Wei Chen, Yi-Yu Liu
ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
14 years 3 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
DAC
2006
ACM
14 years 2 months ago
A high density, carbon nanotube capacitor for decoupling applications
We present a novel application for carbon nanotube devices, implementing a high density 3-D capacitor, which can be useful for decoupling applications to reduce supply voltage var...
Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal...
ISQED
2005
IEEE
133views Hardware» more  ISQED 2005»
14 years 2 months ago
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...
Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao ...
ASPDAC
2005
ACM
127views Hardware» more  ASPDAC 2005»
14 years 2 months ago
Clock network minimization methodology based on incremental placement
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...