1093 search results - page 168 / 219 » Verifying VLSI Circuits |
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
— Many CAD for VLSI problems can be naturally encoded as Quantified Boolean Formulas (QBFs) and solved with QBF solvers. Furthermore, such problems often contain circuitbased in...
VTS
2002
IEEE
14 years 1 months ago
2002
IEEE
Run-length codes and their variants have recently been shown to be very effective for compressing system-on-achip (SOC) test data. In this paper, we analyze the Golomb code, the c...
VTS
2002
IEEE
14 years 1 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
ASPDAC
2007
ACM
14 years 25 days ago
2007
ACM
Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of pow...
INTEGRATION
2007
13 years 8 months ago
2007
In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear p...