1093 search results - page 174 / 219 » Verifying VLSI Circuits |
ISPD
2005
ACM
14 years 2 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
GLVLSI
2003
IEEE
14 years 2 months ago
2003
IEEE
This paper presents a hybrid adiabatic content addressable memory (CAM). The CAM uses an adiabatic switching technique to reduce the energy consumption in the match line while kee...
VLSID
1996
IEEE
14 years 29 days ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
GLVLSI
2007
IEEE
13 years 10 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...